Essential to wafer fabrication technology, photolithography defines the patterns that are transferred to the thin films and other elements that collectively form integrated circuits and other microelectronic devices. Typically, photolithography processing initially includes coating a photoresist material onto a wafer. A “soft-bake” may then be performed, such as to remove solvent from the undeveloped photoresist material. A reticle pattern is then photographically transferred to the photoresist by exposure to electromagnetic radiation through the reticle. A post-exposure bake (PEB) is often employed to complete the chemical reaction initiated by the photographic exposure. The photoresist then undergoes development to remove either the exposed portions of the photoresist (for “positive” photoresist) or the unexposed portions (for “negative” photoresist). Once the photoresist is developed, a “hard-bake” may be performed to further reduce solvent concentrations or adjust selectivity, among other objectives. The resulting pattern of photoresist remaining on the substrate is then employed during selective processing, such as to etch an underlying film by one or more processes to which the photoresist pattern is resistant. Thereafter, the photoresist pattern can be stripped in preparation for further processing, possibly including additional photolithography processing.
However, as the scale of devices manufactured by photolithographic processing continues decrease, conventional photolithography presents an increasing number of obstacles. For example, processing windows continue to shrink, wreaking havoc on production ability and yield. Shrinking feature dimensions are also requiring continually increasing resolution during photolithography, such that conventional photolithographic methods are now becoming known as low-resolution, often delaying the advent of further advances in other processing areas. As feature dimensions are scaled beyond the capabilities of existing photolithography, maintaining the parallelism of sidewalls of vias and other vertically extending features, as well as their perpendicularity or other desired orientation relative to horizontally extending features (e.g., substrates and material layers deposited thereon) are becoming progressively uncontrollable. This results in tapered and other undesired profiles of myriad features, whether at the active device level or in the interconnect structure thereof, which can compound exponentially, further decreasing yield and product quality.